functional block diagram AD7233 dac latch v dd v ss 12 12 gnd ldac sdin sclk sync 12-bit dac 2r 2r v out input shift register rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 12-bit serial mini-dip dacport AD7233 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 general description the AD7233 is a complete 12-bit, voltage-output, digital-to- analog converter with output amplifier and zener voltage refer- ence all in an 8-pin package. no external trims are required to achieve full specified performance. the data format is 2s com- plement, and the output range is C5 v to +5 v. the AD7233 features a fast, versatile serial interface which al- lows easy connection to both microcomputers and 16-bit digital signal processors with serial ports. when the sync input is taken low, data on the sdin pin is clocked into the input shift register on each falling edge of sclk. on completion of the 16-bit data transfer, bringing ldac low updates the dac latch with the lower 12 bits of data and updates the output. alterna- tively, ldac can be tied permanently low, and in this case the dac register is automatically updated with the contents of the shift register when all sixteen data bits have been clocked in. the serial data may be applied at rates up to 5 mhz allowing a dac update rate of 300 khz. for applications which require greater flexibility and unipolar output ranges with single supply operation, please refer to the ad7243 data sheet. the AD7233 is fabricated on linear compatible cmos (lc 2 mos), an advanced, mixed-technology process. it is pack- aged in an 8-pin dip package. dacport is a registered trademark of analog devices, inc. product highlights 1. complete 12-bit dacport ? . 2. the AD7233 is a complete, voltage output, 12-bit dac on a single chip. this single-chip design is inherently more reli- able than multichip designs. 3. simple 3-wire interface to most microcontrollers and dsp processors. 4. dac update rate300 khz. 5. space saving 8-pin package. features 12-bit cmos dac with on-chip voltage reference output amplifier C5 v to +5 v output range serial interface 300 khz dac update rate small size: 8-pin mini-dip nonlinearity: 6 1/2 lsb t min to t max low power dissipation: 100 mw typ applications process control industrial automation digital signal processing systems input/output ports
rev. 0 C2C AD7233Cspecifications 1 (v dd = +12 v to +15 v, 2 v ss = C12 v to C15 v, 2 gnd = 0 v, r l = 2 k v , c l = 100 pf to gnd. all specifications t min to t max unless otherwise noted.) parameter a b units test conditions/comments static performance resolution 12 12 bits relative accuracy 3 1 1/2 lsb max differential nonlinearity 3 0.9 0.9 lsb max guaranteed monotonic bipolar zero error 3 6 6 lsb max dac latch contents 0000 0000 0000 full-scale error 3 8 8 lsb max full-scale temperature coefficient 30 30 ppm of fsr/ c typ digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i in 1 1 m a max v in = 0 v to v dd input capacitance 4 8 8 pf max analog outputs output voltage range 5 5v dc output impedance 0.5 0.5 w typ ac characteristics 4 voltage output settling time settling time to within 1/2 lsb of final value positive full-scale change 10 10 m s max typically 3 m s; dac latch 100. . .000 to 011. . .111 negative full-scale change 10 10 m s max typically 5 m s; dac latch 011. . .111 to 100. . .000 digital-to-analog glitch impulse 3 30 30 nv secs typ dac latch contents toggled between all 0s and all 1s digital feedthrough 3 10 10 nv secs typ ldac = high power requirements v dd range +10.8/+16.5 +11.4/+15.75 v min/v max for specified performance unless otherwise stated v ss range C10.8/C16.5 C11.4/C15.75 v min/v max for specified performance unless otherwise stated i dd 10 10 ma max output unloaded; typically 7 ma i ss 4 4 ma max output unloaded; typically 2 ma notes 1 temperature ranges are as follows: a, b versions: C40 c to +85 c. 2 power supply tolerance: a version: 10%; b version: 5%. 3 see terminology. 4 sample tested @ +25 c to ensure compliance. specifications subject to change without notice. timing characteristics 1, 2 limit at +25 8 c limit at t min , t max parameter (all versions) (all versions) units conditions/comments t 1 3 200 200 ns min sclk cycle time t 2 50 50 ns min sync to sclk falling edge setup time t 3 120 190 ns min sync to sclk hold time t 4 10 10 ns min data setup time t 5 100 100 ns min data hold time t 6 0 0 ns min sync high to ldac low t 7 50 50 ns min ldac pulse width t 8 0 0 ns min ldac high to sync low notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr and tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figure 3. 3 sclk mark/space ratio range is 40/60 to 60/40. (v dd = +10.8 v to +16.5 v, v ss = C10.8 v to C16.5 v, gnd = o v, r l = 2 k v , c l = 100 pf. all specifications t min to t max unless otherwise noted.)
AD7233 rev. 0 C3C absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +17 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C17 v v out 2 to gnd . . . . . . . . . . . . . . . . . . . . . C6 v to v dd +0.3 v digital inputs to gnd . . . . . . . . . . . . . . C0.3 v to v dd +0.3 v operating temperature range industrial (a, b versions) . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c power dissipation to +75 c . . . . . . . . . . . . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 the output may be shorted to voltages in this range provided the power dissipation of the package is not exceeded. short circuit current is typically 80 ma. ordering guide temperature relative package model range accuracy option* AD7233an C40 c to +85 c 1 lsb n-8 AD7233bn C40 c to +85 c 1/2 lsb n-8 *n = plastic dip. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7233 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. terminology relative accuracy (linearity) relative accuracy, or endpoint linearity, is a measure of the maximum deviation of the dac transfer function from a straight line passing through the endpoints of the transfer function. it is measured after allowing for zero and full-scale errors and is ex- pressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb or less over the operating temperature range ensures monotonicity. bipolar zero error bipolar zero error is the voltage measured at v out when the dac is loaded with all 0s. it is due to a combination of offset errors in the dac, amplifier and mismatch between the internal gain resistors around the amplifier. full-scale error full-scale error is a measure of the output error when the am- plifier output is at full scale (full scale is either positive or nega- tive full scale). digital-to-analog glitch impulse this is the voltage spike that appears at the output of the dac when the digital code in the dac latch changes before the out- put settles to its final value. the energy in the glitch is specified in nv secs, and is measured for an all codes change (0000 0000 0000 to 1111 1111 1111). digital feedthrough this is a measure of the voltage spike that appears on v out as a result of feedthrough from the digital inputs on the AD7233. it is measured with ldac held high.
AD7233 rev. 0 C4C pin function description pin mnemonic description 1v dd positive supply (+12 v to +15 v). 2 sclk serial clock, logic input. data is clocked into the input register on each falling sclk edge. 3 sdin serial data in, logic input. the 16-bit serial data word is applied to this input. 4 sync data synchronization pulse, logic input. taking this input low initializes the internal logic in readiness for a new data word. 5 ldac load dac, logic input. updates the dac output. the dac output is updated on the falling edge of this signal, or alternatively if this line in permanently low, an automatic update mode is selected whereby the dac is updated on the 16th falling sclk pulse. 6 gnd ground pin = 0 v. 7v out analog output voltage. this is the buffered dac output voltage (C5 v to +5 v). 8v ss negative supply (C12 v to C15 v). digital interface the AD7233 contains an input serial to parallel shift register and a dac latch. a simplified diagram of the input loading cir- cuitry is shown in figure 2. serial data on the sdin input is loaded to the input register under control of sync and sclk. when a complete word is held in the shift register it may then be loaded into the dac latch under control of ldac . only the data in the dac latch determines the analog output on the AD7233. a low sync input provides the frame synchronization signal which tells the AD7233 that valid serial data on the sdin input will be available for the next 16 falling edges of sclk. an inter- nal counter/decoder circuit provides a low gating signal so that only 16 data bits are clocked into the input shift register. after 16 sclk pulses the internal gating signal goes inactive (high) thus locking out any further clock pulses. therefore, either a continuous clock or a burst clock source may be used to clock in the data. the sync input should be taken high after the complete 16-bit word is loaded in. although 16 bits of data are clocked into the input register, only the latter 12 bits get transferred into the dac latch. the first 4 bits in the 16-bit stream are dont cares since their value does not affect the dac latch data. therefore the data format is 4 dont cares followed by the 12-bit data word with the lsb as the last bit in the serial stream. circuit information d/a section the AD7233 contains a 12-bit voltage-mode d/a converter consisting of highly stable thin-film resistors and high speed nmos single-pole, double-throw switches. op amp section the output of the voltage-mode d/a converter is buffered by a noninverting cmos amplifier. the buffer amplifier is capable of developing 5 v across a 2 k w load to gnd. 2r r 2r r r 2r 2r v out gnd 2r 2r 2r db0 db1 db9 db10 db11 2r rr internal reference 5v figure 1. simplified d/a converter v out ldac 2 3 4 5 6 7 8 AD7233 top view (not to scale) gnd sdin sclk v ss v dd sync 1
AD7233 rev. 0 C5C there are two ways in which the dac latch and hence the ana- log output may be updated. the status of the ldac input is examined after sync is taken low. depending on its status, one of two update modes is selected. if ldac = 0 then the automatic update mode is selected. in this mode the dac latch and analog output are updated auto- matically when the last bit in the serial data stream is clocked in. the update thus takes place on the sixteenth falling sclk edge. if ldac = 1 then the automatic update is disabled and the dac latch is updated by taking ldac low any time after the 16-bit data transfer is complete. the update now occurs on the falling edge of ldac . this facility is useful for simultaneous update in multi-dac systems. note that the ldac input must be taken back high again before the next data transfer is initiated. reset sclk ?6 counter/ decoder gating signal gated sclk sdin input shift register (16 bits) dac latch (12 bits) sync ldac auto-update circuitry figure 2. simplified loading structure sclk sdin t 4 t 1 t 3 t 2 t 5 db15 don't care db0 lsb sync ldac db11 msb db14 don't care db13 don't care db12 don't care t 6 t 7 t 8 ? db1 ? ? ? ? figure 3. timing diagram
AD7233Ctypical performance graphs rev. 0 C6C applying the AD7233 bipolar ( 6 5 v) configuration the AD7233 provides an output voltage range from C5 v to +5 v without any external components. this configuration is shown in figure 4. the data format is 2s complement. the out- put code table is shown in table i. if offset binary coding is re- quired, then this can be done by inverting the msb in software before the data is loaded to the AD7233. AD7233 v dd v ss gnd 12-bit dac 2r 2r v out +15v ?5v +5v +12v to ?2v to figure 4. circuit configuration power supply decoupling to achieve optimum performance when using the AD7233, the v dd and v ss lines should each be decoupled to gnd using 0.1 m f capacitors. in very noisy environments it is recom- mended that 10 m f capacitors be connected in parallel with the 0.1 m f capacitors. table i. AD7233 bipolar code table input data word msb lsb analog output, v out xxxx 0111 1111 1111 +5 v ? (2047/2048) xxxx 0000 0000 0001 +5 v ? (1/2048) xxxx 0000 0000 0000 0 v xxxx 1111 1111 1111 C5 v ? (1/2048) xxxx 1000 0000 0001 C5 v ? (2047/2048) xxxx 1000 0000 0000 C5 v ? (2048/2048) = C5 v x = dont care note: 1 lsb = 5 v/2048 ? 2.4 mv 100 0 100k 20 10 1k 10 40 30 50 60 70 80 90 100 10k frequency ?hz psrr ?db output with all 0s on dac decoupling decoupling no decoupling output with all 1s on dac no decoupling v = +15v with 100mv p? signal dd power supply decoupling capacitors are 10 m f and 0.1 m f. * power supply rejection ratio vs. frequency 0.50 0 16 0.10 13 10.5 0.20 0.30 0.40 11 12 14 15 t = +25 c a v /v ?volts dd linearity ?lsbs ss linearity vs. power supply voltage 500 0 100k 20 5k 50 50 100 200 100 200 500 1k 2k 10k 20k 50k frequency ?hz nv/ hz output with all 0s on dac v = +15v v = ?15v t = +25 c dd ss a noise spectral density vs. frequency
AD7233 rev. 0 C7C microprocessor interfacing microprocessor interfacing to the AD7233 is via a serial bus which uses standard protocol compatible with dsp processors and microcontrollers. the communications channel requires a three-wire interface consisting of a clock signal, a data signal and a synchronization signal. the AD7233 requires a 16-bit data word with data valid on the falling edge of sclk. for all of the interfaces, the dac update may be done automatically when all the data is clocked in or it may done under control of ldac . figures 5 to 8 show the AD7233 configured for interfacing to a number of popular dsp processors and microcontrollers. AD7233Cadsp-2101/adsp-2102 interface figure 5 shows a serial interface between the AD7233 and the adsp-2101/adsp-2102 dsp processor. the adsp-2101/ adsp-2102 contains two serial ports, and either port may be used in the interface. the data transfer is initiated by tfs going low. data from the adsp-2101/adsp-2102 is clocked into the AD7233 on the falling edge of sclk. when the data transfer is complete tfs is taken high. in the interface shown the dac is updated using an external timer which generates an ldac pulse. this could also be done using a control or decoded ad- dress line from the processor. alternatively, the ldac input could be hardwired low, and in this case the automatic update mode is selected whereby the dac update takes place automati- cally on the 16th falling edge of sclk. timer ldac adsp-2101/ adsp-2102* sdin sclk * additional pins omitted for clarity sync sclk dt AD7233* tfs figure 5. AD7233 to adsp-2101/adsp-2102 interface AD7233-dsp56000 interface a serial interface between the AD7233 and the dsp56000 is shown in figure 6. the dsp56000 is configured for normal mode asynchronous operation with gated clock. it is also set up for a 16-bit word with sck and sc2 as outputs and the fsl control bit set to a 0. sck is internally generated on the dsp56000 and applied to the AD7233 sclk input. data from the dsp56000 is valid on the falling edge of sck. the sc2 output provides the framing pulse for valid data. this line must be inverted before being applied to the sync input of the AD7233. the ldac input of the AD7233 is connected to gnd so the update of the dac latch takes place automatically on the 16th falling edge of sclk. an external timer could also be used as in the previous interface if an external update is required. ldac dsp56000 sclk sdin sck std * additional pins omitted for clarity AD7233* sc2 sync figure 6. AD7233 to dsp56000 interface AD7233C87c51 interface a serial interface between the AD7233 and the 87c51 micro- controller is shown in figure 7. txd of the 87c51 drives sclk of the AD7233 while rxd drives the serial data line of the part. the sync signal is derived from the port line p3.3. the 87c51 provides the lsb of its sbuf register as the first bit in the serial data stream. therefore, the user will have to ensure that the data in the sbuf register is arranged correctly so that the dont care bits are the first to be transmitted to the AD7233 and the last bit to be sent is the lsb of the word to be loaded to the AD7233. when data is to be transmitted to the part, p3.3 is taken low. data on rxd is valid on the falling edge of txd. the 87c51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. to load data to the AD7233, p3.3 is kept low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7233. when the second serial transfer is complete, the p3.3 line is taken high. figure 7 shows the ldac input of the AD7233 hardwired low. as a result, the dac latch and the analog output will be up- dated on the sixteenth falling edge of txd after the sync sig- nal for the dac has gone low. alternatively, the scheme used in previous interfaces, whereby the ldac input is driven from a timer, can be used. ldac 87c51* sdin txd * additional pins omitted for clarity sync sclk rxd AD7233* p3.3 figure 7. AD7233 to 87c51 interface
AD7233 rev. 0 C8C c1494C10C1/91 printed in u.s.a. AD7233-68hc11 interface figure 8 shows a serial interface between the AD7233 and the 68hc11 microcontroller. sck of the 68hc11 drives sclk of the AD7233 while the mosi output drives the serial data line. the sync signal is derived from a port line (pc7 shown). for correct operation of this interface, the 68hc11 should be configured such that its cpol bit is a 0 and its cpha bit is a 1. when data is to be transmitted to the part, pc7 is taken low. when the 68hc11 is configured like this, data on mosi is valid on the falling edge of sck. the 68hc11 transmits its se- rial data in 8-bit bytes with only eight falling clock edges occur- ring in the transmit cycle. to load data to the AD7233, pc7 is kept low after the first eight bits are transferred and a second byte of data is then transferred serially to the AD7233. when the second serial transfer is complete, the pc7 line is taken high. figure 8 shows the ldac input of the AD7233 hard- wired low. as a result, the dac latch and the analog output of the dac will be updated on the sixteenth falling edge of sck after the respective sync signal has gone low. alternatively, the scheme used in previous interfaces, whereby the ldac in- put is driven from a timer, can be used. ldac 68hc11* sdin sck * additional pins omitted for clarity sync sclk mosi AD7233* pc7 figure 8. AD7233 to 68hc11 interface outline dimensions dimensions shown in inches and (mm). plastic dip (n-8) package 0.195 (4.95) max 8 1 5 4 0.210 (5.33) max 0.150 (3.81) min 0.100 bsc (2.54 bsc) 0.240 (6.10) 0.280 (7.11) 0.348 (8.84) 0.430 (10.92) 0.015 (0.38) 0.060 (1.52) 0.045 (1.15) 0.70 (1.77) 0.014 (0.356) 0.022 (0.558) 0.300 (7.62) 0.325 (8.25) 0.008 (0.204) 0.015 (0.381)
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